// ========================================================================================
// FileName : Intro_Top.v:  Top level of a simple design.
//
// This module contains the top structure of the design, which is made up of three 
// lower-level modules and one inverter gate.
// The structure is represented by module instances.
//
// JTAG port and FF's added for Lab05, through Step3.
// ---------------------------------------------------------------------------------------
// Author   : QilinZhao
// Version  : v-1.0
// Date     : 2013-08-29
// E-mail   : forqilin@163.com
// Copyright: QiXin Studio
// =======================================================================================

module Intro_Top ( output X, Y, Z, input A, B, C, D,
                   output ScanOut,
                   input ScanMode, ScanIn, ScanClr, ScanClk
                 );
wire ab, bc, q, qn;  // Wires for internal connectivity.

// New FF wires:
wire X_to_FFX, Y_to_FFY, Z_to_FFZ
   , FFA_to_A, FFB_to_B, ffc_to_C, FFD_to_D;

assign #1 Z_to_FFZ = ~qn; // Inverter by continuous assignment statement.

AndOr InputCombo  (.X(ab), .Y(bc), .A(FFA_to_A), .B(FFB_to_B), .C(ffc_to_C));
   SR SRLatch     (.Q(q), .Qn(qn), .S(bc), .R(FFD_to_D));
XorNor OutputCombo (.X(X_to_FFX), .Y(Y_to_FFY), .A(ab), .B(q), .C(qn));

// New FF's:
// The ffc model has a Qn output, but unconnected outputs simply may be omitted.
ffc FF_X(.Q(X),        .Qn(), .D(X_to_FFX), .Clk(ScanClk), .Clr(ScanClr));
ffc FF_Y(.Q(Y),        .Qn(), .D(Y_to_FFY), .Clk(ScanClk), .Clr(ScanClr));
ffc FF_Z(.Q(Z),        .Qn(), .D(Z_to_FFZ), .Clk(ScanClk), .Clr(ScanClr));
ffc FF_A(.Q(FFA_to_A), .Qn(), .D(A),        .Clk(ScanClk), .Clr(ScanClr));
ffc FF_B(.Q(FFB_to_B), .Qn(), .D(B),        .Clk(ScanClk), .Clr(ScanClr));
ffc FF_C(.Q(ffc_to_C), .Qn(), .D(C),        .Clk(ScanClk), .Clr(ScanClr));
ffc FF_D(.Q(FFD_to_D), .Qn(), .D(D),        .Clk(ScanClk), .Clr(ScanClr));

endmodule // Intro_Top
